1. Field of the Invention
The present invention relates generally to semiconductors and more specifically to a circuit and method for preventing latch-up occurrence in a CMOS semiconductor device.
2. Background Art
"Latch-up" is an undesired silicon controlled rectifier action which can lead to the destruction or malfunction of an integrated circuit CMOS semiconductor device 100, which is shown in FIG. 1. In addition, latch-up can destroy a power supply 103 providing the V.sub.CC power supply voltage to CMOS semiconductor device 100. Latch-up typically occurs when a parasitic bipolar transistor circuit 105, which is inherent in a CMOS semiconductor device 100, turns on during the initial application (or power-on) of power supply 103 and remains on after removal of the signal which triggers the forward biasing of parasitic bipolar transistor circuit 105.
Parasitic bipolar transistor circuit 105 includes the following: a parasitic pnp bipolar junction transistor 110, a parasitic npn bipolar junction transistor 115, resistors 120, 125, and 130 representing the equivalent resistance of an n-type substrate 135, and a resistor 140 representing the equivalent resistance of a p-well region 145. (FIG. 2 shows parasitic bipolar transistor circuit 105 in an equivalent circuit model.)
The V.sub.CC voltage level is tied to the voltage level of a p+ diffusion 150 of a p-channel transistor (not shown) in CMOS semiconductor device 100. The V.sub.SS voltage level is tied to the voltage level of an n+ diffusion 152 of an n-channel transistor (not shown) in CMOS semiconductor device 100.
Reference is now made to both FIGS. 1 and 2. Two conditions are required to trigger latch-up in CMOS semiconductor device 100. The first condition is for the n-type substrate 135 voltage, "V.sub.NN," to fall to at least one diode drop or "VD.sub.(on) " (typically 0.6 volts) below the V.sub.CC voltage level. As known by those skilled in the art, the VD.sub.(on) voltage value is alternatively named as the "bipolar transistor turn-on voltage", the "diode turn-on voltage", or "VBE.sub.(on) ". When this first condition occurs (i.e., V.sub.NN falls below V.sub.CC by at least one diode drop), an unwanted trigger current 155 generates and flows between the emitter-base junction of parasitic pnp bipolar junction transistor 110. This unwanted trigger current 155 will cause parasitic pnp bipolar junction transistor 110 to become forward biased. Since parasitic pnp bipolar junction transistor 110 becomes forward biased, it generates a second trigger current 160 which flows between the emitter-base junction of parasitic npn bipolar junction transistor 115.
The second condition required for latch-up is for the p-well region 145 voltage, "V.sub.BB," to rise to at least one VD.sub.(on) above the V.sub.SS ground or reference potential. When this second condition occurs, then second trigger current 160 can cause parasitic npn bipolar junction transistor 115 to become forward biased. When parasitic pnp bipolar junction transistor 110 and parasitic npn bipolar junction transistor 115 become forward biased, latch-up occurs in CMOS semiconductor device 100.
If latch-up occurs, CMOS semiconductor device 100 will remain "on" even after unwanted trigger currents 155 and 160 are removed. Eventually, power supply 103 can short-circuit to the V.sub.SS reference potential, thereby leading to the destruction or malfunction of CMOS semiconductor device 100 and/or of power supply 103 itself.
As supply voltages have scaled down, it is also becoming common to use charge pumps for boosting the V.sub.CC supply voltage level and the V.sub.NN n-type substrate voltage level in a CMOS semiconductor device. This is particularly important in semiconductor memories such as SRAMS, DRAMs, and EEPROMS. In order to combat leakage currents in memory cells, it is common to use charge pumps for applying a negative bias voltage to the well region surrounding the memory array. However, the use of charge pumps increases the likelihood of latch-up, since it is possible for the substrate and well junction to become forward biased during the power-on condition. Thus, there is a need for a circuit for preventing latch-up in these charge pump based circuits.
One method to prevent latch-up in CMOS semiconductor devices is by applying a negative biasing voltage (commonly known as "back-bias voltage") to p-well region 145. Back-bias circuits or methods are shown and described in U.S. Pat. Nos. 4,794,278, 4,647,956, 5,545,934, and 5,220,534, all of which are fully incorporated herein by reference thereto as if fully reproduced immediately hereinafter. The negative back-bias voltage causes the emitter-base junction of parasitic npn bipolar junction transistor 115 to become reversed biased. This additional negative voltage provided by the back-bias voltage to p-well region 145 prevents the forward biasing of the emitter-base junction of parasitic npn bipolar junction transistor 115, thereby decreasing the probability of latch-up.
Another method to decrease the probability of latch-up is by increasing the impurity doping in p-well region 145, thereby decreasing minority carrier lifetime in the base region of parasitic npn bipolar junction transistor 115. However, this particular method leads to higher capacitance and to slower operating speeds of CMOS semiconductor device 100, as noted in Price, Betty, Semiconductor Memories, John Wiley & Sons, New York, N.Y. (2nd ed. 1991), which is fully incorporated herein by reference thereto as if fully reproduced immediately hereinafter. Still another method for decreasing the probability of latch-up is by using guard rings on p-well region 145. However, guard rings require additional space and will, therefore, increase the size of CMOS semiconductor device 100.
In addition, the conventional approaches mentioned above do not address the condition after initial power-up when the V.sub.CC voltage level has already risen to, for example, the V.sub.TH voltage level and when V.sub.CC has risen above the V.sub.NN voltage level. The V.sub.TH voltage is also known as the MOS transistor threshold voltage and is typically in the range from about 0.6V to about 0.8V. As the V.sub.CC voltage level rises, it may rise faster than the V.sub.NN voltage level, thereby leading to voltage value differences between V.sub.CC and V.sub.NN. When the V.sub.CC voltage level rises above the V.sub.NN voltage level, trigger current 155 may have a sufficient value to forward bias parasitic npn bipolar junction transistor 115, even if a negative bias voltage is being applied to p-well region 145 for reverse biasing parasitic npn bipolar junction transistor 115. Conventional approaches, therefore, do not decrease the probability of latch-up when the V.sub.CC supply voltage level has risen above or is rising above very low levels.
Thus, there remains a need for a circuit and method that overcome the foregoing deficiencies and prevent the problem of latch-up in a CMOS semiconductor device.